TSMC was charging chip designers $20,000 for every silicon wafer used to supply a 3nm chipset. Every wafer can produce 300 to 400 chips. At $30,000, the wafer used for 2nm manufacturing is 50% dearer than the $20,000 TSMC charged for the wafer utilized in 3nm manufacturing. It’s twice as costly because the $15,000 charged for the wafers utilized in TSMC’s 4nm and 5nm manufacturing. Going again much more, in 2014 TSMC charged purchasers $3,000 for wafers used to construct its 28nm chips.
The 2nm node will debut a few new options for chips constructed by TSMC. The foundry’s 2nm chips will use nanosheet Gate-all-around (GAA) transistors to interchange FinFET. With GAA, the gate comes into contact with the channel on all sides decreasing present leakage and enhancing the drive present. This ends in a ten% to fifteen% energy enhance, a 15% transistor density enhance, and a 25% to 30% discount in energy consumption.
TSMC’s 2nm manufacturing may even embrace bottom energy supply (BPD) which strikes the ability connections to the again aspect of the chip permitting them to be shorter than the connections used with conventional frontside energy supply. This ends in a discount in energy loss from line resistance. The underside line is a 15%-20% enchancment in energy utilization.
